VLSI Interview Questions
Explain about high speed CMOS circuits ?
What is VHDL and Verilog?
In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
What is meant by term snooping?
What is meant by the term MESI?
Explain the difference between write through and write back cache. ?
What are the main issues associated with multiprocessor caches and how they can be solved ?
Explain the operation considering a two processor computer system with a cache for each
processor ?
For a single computer processor computer system, what is the purpose of a processor cache and
describe its operation?
How many bit combinations are there in a byte?
Explain about pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what
is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
Explain the Insights of a Tri-State Inverter?
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR?
Why?
Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
Differences between Array and Booth Multipliers?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
What is Fowler-Nordheim Tunneling?
Implement an Inverter using a single transistor?
What is clock feed through?
What are the phenomenon which come into play when the devices are scaled to the sub-micron
lengths?
Different ways of implementing a comparator?
What is Cross Talk?
What is validation?
Who provides the DRC rules?
What is LVS, DRC?
Why is Extraction performed?
Explain Custom Design Flow?
Explain ASIC Design Flow?
Explain the Various steps in Synthesis?
Explain the various Capacitances associated with a transistor and which one of them is the most
prominent?
Why do we use a Clock tree?
Explain Clock Skew?
Factors affecting Power Consumption on a chip?
Define threshold voltage?
What is hot electron effect?
What is component binding?
Differences between functions and Procedures in VHDL?
Differences between Signals and Variables in VHDL? If the same code is written using Signals
and Variables what does it synthesize to?
Differences between blocking and Non-blocking statements in Verilog?
What is 6-T XOR gate?
Explain the Working of a 2-stage OPAMP?
Implement F = AB+C using CMOS gates?
If the current through the poly is 20nA and the contact can take a maximum current of 10nA
how would you overcome the problem?
Draw the Layout of an Inverter?
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly,
M1 and diffusion layers etc?
What is FPGA?
Differences between netlist of HSPICE and Spectre?
Differences between IRSIM and SPICE?
What is SPICE?
Explain about stuck at fault models, scan design, BIST and IDDQ testing?
What is pipelining and how can we increase throughput using pipelining?
Write a pseudo code for sorting the numbers in an array?
What is setup time and hold time?
What happens when the gate oxide is very thin?
How can you construct both PMOS and NMOS on a single substrate?
Implement a function with both rationed and domino logic and merits and demerits of each
logic?
List out the differences between DRAM and SRAM?
Explain the operation of a 6T-SRAM cell?
Explain Id vs. Vds Characteristics of NMOS and PMOS transistors?
Give an Advantages and disadvantages of Mealy and Moore?
A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW
for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
Explain the working of 4-bit Up/down Counter?
Explain various adders and differences between them?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
What are the Insights of a 4bit adder/Sub Circuit?
Implement a 2 I/P and gate using Tran gates?
What is a linked list? Explain the 2 fields in a linked list?
While using logic design, explain the various steps that are followed to obtain the desirable
design in a well defined manner?
What is charge sharing?
What is latchup? Explain the methods used to prevent it?
Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
Differences between D-Latch and D flip-flop?
What is a D-latch? Write the VHDL Code for it?
Explain the Cross section of an NMOS transistor?
Explain the Cross section of a PMOS transistor?
What does the above code synthesize to?
Why do we need both PMOS and NMOS transistors to implement a pass gate?
Implement F= not (AB+CD) using CMOS gates?
What are the Insights of a 2 input NAND gate. Explain the working?
What are the Insights of a 2 input NOR gate. Explain the working?
Explain the Insights of an inverter and its working?
What transistor level design tools are you proficient with? What types of designs were they used
on?
Explain the difference between write through and write back cache ?
What are the main issues associated with multiprocessor caches and how might you solve them?
Explain the operation considering a two processor computer system with a cache for each
processor ?
For a single computer processor computer system, what is the purpose of a processor cache and
describe its operation?
What is interrupt latency?
How do you detect if two 8-bit signals are same?
What are set up time and hold time constraints? What do they signify?
Suppose you have a combinational circuit between two registers driven by a clock. What will you
do if the delay of the combinational circuit is greater than your clock signal? Explain the usage of
the shared SPI bus?
How to find the read failure probability in SRAM?
What are the ways to Optimize the Performance of a Difference Amplifier?
How can you model a SRAM at RTL Level?
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
What is the critical path in a SRAM?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Explain the Charge Sharing problem while sampling data from a Bus?
Give the various techniques you know to minimize power consumption?
What happens if we increase the number of contacts or via from one metal layer to the next?
How does Resistance of the metal lines vary with increasing thickness and increasing length?
What are the limitations in increasing the power supply to reduce delay?
What happens to delay if you increase load capacitance?
What is Body Effect?
Give the expression for CMOS switching power dissipation?
What is Noise Margin? Explain the procedure to determine Noise Margin?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Explain sizing of the inverter?
Explain CMOS Inverter transfer characteristics?
Explain the various MOSFET Capacitances & their significance?
Explain why & how a MOSFET works?
Explain the Charge Sharing problem while sampling data from a Bus?
What happens if we delay the enabling of Clock signal?
What is Latch up? How to avoid Latch up?
How can you model a SRAM at RTL Level?
What is the difference between Testing & Verification?
What happens if we delay the enabling of Clock signal?
What is the critical path in a SRAM?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Explain the working of differential sense amplifier?
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
What is charge sharing?
Give the expression for calculating Delay in CMOS circuit?
What happens to delay if we include a resistance at the output of a CMOS circuit?
What are the different limitations in increasing the power supply to reduce delay?
What happens to delay if you increase load capacitance?
Give the expression for CMOS switching power dissipation?
What is Noise Margin? Explain the procedure to determine Noise Margin?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Explain the sizing of the inverter?
Explain the various MOSFET Capacitances & their significance ?
Explain how MOSFET works?
How to improve these parameters? (Cascode topology, use long channel transistors)
How about voltage source?
What is short Channel effect ?
What is Early effects and their physical origin ?
Explain the working of BJT ?
What is the ideal input and output resistance of a current source?
How does a Bandgap Voltage reference work?
For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?
Explain how MOSFET works ?
What is the build-in potential?
What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).
What is the depletion region?
How does a pn junction works?
What is the doping?
What is Channel length modulation?
If the substrate doping concentration increase, or temperature increases, how will Vt change? it
increase or decrease?
How does Vbe and Ic change with temperature?
What is Fermi level?
What is conductance and valence band?
What is VHDL and Verilog?
In what cases do you need to double clock a signal before presenting it to a synchronous state machine?
What is meant by term snooping?
What is meant by the term MESI?
Explain the difference between write through and write back cache. ?
What are the main issues associated with multiprocessor caches and how they can be solved ?
Explain the operation considering a two processor computer system with a cache for each
processor ?
For a single computer processor computer system, what is the purpose of a processor cache and
describe its operation?
How many bit combinations are there in a byte?
Explain about pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what
is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
Explain the Insights of a Tri-State Inverter?
Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR?
Why?
Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
Differences between Array and Booth Multipliers?
If an/ap = 0.5, an/ap = 1, an/ap = 3, for 3 inverters draw the transfer characteristics?
What is Fowler-Nordheim Tunneling?
Implement an Inverter using a single transistor?
What is clock feed through?
What are the phenomenon which come into play when the devices are scaled to the sub-micron
lengths?
Different ways of implementing a comparator?
What is Cross Talk?
What is validation?
Who provides the DRC rules?
What is LVS, DRC?
Why is Extraction performed?
Explain Custom Design Flow?
Explain ASIC Design Flow?
Explain the Various steps in Synthesis?
Explain the various Capacitances associated with a transistor and which one of them is the most
prominent?
Why do we use a Clock tree?
Explain Clock Skew?
Factors affecting Power Consumption on a chip?
Define threshold voltage?
What is hot electron effect?
What is component binding?
Differences between functions and Procedures in VHDL?
Differences between Signals and Variables in VHDL? If the same code is written using Signals
and Variables what does it synthesize to?
Differences between blocking and Non-blocking statements in Verilog?
What is 6-T XOR gate?
Explain the Working of a 2-stage OPAMP?
Implement F = AB+C using CMOS gates?
If the current through the poly is 20nA and the contact can take a maximum current of 10nA
how would you overcome the problem?
Draw the Layout of an Inverter?
Draw the Cross Section of an Inverter? Clearly show all the connections between M1 and poly,
M1 and diffusion layers etc?
What is FPGA?
Differences between netlist of HSPICE and Spectre?
Differences between IRSIM and SPICE?
What is SPICE?
Explain about stuck at fault models, scan design, BIST and IDDQ testing?
What is pipelining and how can we increase throughput using pipelining?
Write a pseudo code for sorting the numbers in an array?
What is setup time and hold time?
What happens when the gate oxide is very thin?
How can you construct both PMOS and NMOS on a single substrate?
Implement a function with both rationed and domino logic and merits and demerits of each
logic?
List out the differences between DRAM and SRAM?
Explain the operation of a 6T-SRAM cell?
Explain Id vs. Vds Characteristics of NMOS and PMOS transistors?
Give an Advantages and disadvantages of Mealy and Moore?
A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1. If X = LOW
for 4 clock ticks, B = 1. Draw a state diagram for this Spec?
Explain the working of 4-bit Up/down Counter?
Explain various adders and differences between them?
For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault?
What are the Insights of a 4bit adder/Sub Circuit?
Implement a 2 I/P and gate using Tran gates?
What is a linked list? Explain the 2 fields in a linked list?
While using logic design, explain the various steps that are followed to obtain the desirable
design in a well defined manner?
What is charge sharing?
What is latchup? Explain the methods used to prevent it?
Implement D flip-flop with a couple of latches? Write a VHDL Code for a D flip-flop?
Differences between D-Latch and D flip-flop?
What is a D-latch? Write the VHDL Code for it?
Explain the Cross section of an NMOS transistor?
Explain the Cross section of a PMOS transistor?
What does the above code synthesize to?
Why do we need both PMOS and NMOS transistors to implement a pass gate?
Implement F= not (AB+CD) using CMOS gates?
What are the Insights of a 2 input NAND gate. Explain the working?
What are the Insights of a 2 input NOR gate. Explain the working?
Explain the Insights of an inverter and its working?
What transistor level design tools are you proficient with? What types of designs were they used
on?
Explain the difference between write through and write back cache ?
What are the main issues associated with multiprocessor caches and how might you solve them?
Explain the operation considering a two processor computer system with a cache for each
processor ?
For a single computer processor computer system, what is the purpose of a processor cache and
describe its operation?
What is interrupt latency?
How do you detect if two 8-bit signals are same?
What are set up time and hold time constraints? What do they signify?
Suppose you have a combinational circuit between two registers driven by a clock. What will you
do if the delay of the combinational circuit is greater than your clock signal? Explain the usage of
the shared SPI bus?
How to find the read failure probability in SRAM?
What are the ways to Optimize the Performance of a Difference Amplifier?
How can you model a SRAM at RTL Level?
In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
What is the critical path in a SRAM?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Explain the Charge Sharing problem while sampling data from a Bus?
Give the various techniques you know to minimize power consumption?
What happens if we increase the number of contacts or via from one metal layer to the next?
How does Resistance of the metal lines vary with increasing thickness and increasing length?
What are the limitations in increasing the power supply to reduce delay?
What happens to delay if you increase load capacitance?
What is Body Effect?
Give the expression for CMOS switching power dissipation?
What is Noise Margin? Explain the procedure to determine Noise Margin?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Explain sizing of the inverter?
Explain CMOS Inverter transfer characteristics?
Explain the various MOSFET Capacitances & their significance?
Explain why & how a MOSFET works?
Explain the Charge Sharing problem while sampling data from a Bus?
What happens if we delay the enabling of Clock signal?
What is Latch up? How to avoid Latch up?
How can you model a SRAM at RTL Level?
What is the difference between Testing & Verification?
What happens if we delay the enabling of Clock signal?
What is the critical path in a SRAM?
What happens if we use an Inverter instead of the Differential Sense Amplifier?
Explain the working of differential sense amplifier?
Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
What is charge sharing?
Give the expression for calculating Delay in CMOS circuit?
What happens to delay if we include a resistance at the output of a CMOS circuit?
What are the different limitations in increasing the power supply to reduce delay?
What happens to delay if you increase load capacitance?
Give the expression for CMOS switching power dissipation?
What is Noise Margin? Explain the procedure to determine Noise Margin?
How do you size NMOS and PMOS transistors to increase the threshold voltage?
Explain the sizing of the inverter?
Explain the various MOSFET Capacitances & their significance ?
Explain how MOSFET works?
How to improve these parameters? (Cascode topology, use long channel transistors)
How about voltage source?
What is short Channel effect ?
What is Early effects and their physical origin ?
Explain the working of BJT ?
What is the ideal input and output resistance of a current source?
How does a Bandgap Voltage reference work?
For a 0.18um and 0.8um technology MOSFET, which has a higher cutoff frequency?
Explain how MOSFET works ?
What is the build-in potential?
What are the two types of noise of MOSFET, how to eliminate them?(Thermal and Flicker).
What is the depletion region?
How does a pn junction works?
What is the doping?
What is Channel length modulation?
If the substrate doping concentration increase, or temperature increases, how will Vt change? it
increase or decrease?
How does Vbe and Ic change with temperature?
What is Fermi level?
What is conductance and valence band?
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